The sigma-delta technique is of great interest for realizing linear, accurate and simple analog-to-digital converters. Sigma-delta coders and decoders generally require the use of decimation circuits necessitating a great number of electronic components. For that reason, decimation circuits are embodied by means of Very Large Scale Integrated Technology (VLSI) components.
FIG. 1 shows the traditional basic structure of an analog-to-digital converter which uses a sigma-delta converter (130) for converting an analog input signal existing on a lead 110 in a train of sigma-delta pulses on a lead 120. The train of sigma-delta pulse comprising a high level of out-of-band quantization noise is then entered into a decimation filter 170 for converting the sigma-delta pulses into a sequence of Pulse Coded Modulation (PCM) samples on lead 140. For that purpose, decimation circuit 170 includes a low-pass digital filter 150 for suppressing the above out-of-band quantization and for avoiding in-band aliasing during the decimation process. Decimation circuit 170 also includes the specific decimation element which samples down the output signal of low-pass filter. This is simply achieved by taking one PCM sample over N samples. N is called the decimation factor of the process.
FIG. 2 illustrates a traditional simple-loop sigma-delta converter which is based on an operational amplifier 214 and a D.sub.-- latch 215. The signal to be coded is entered, after an appropriate suppression of the DC component existing on the analog signal by means of a capacitor 210, in an integrator based on OA 214, resistor 211 and capacitor 213. The output of OA 214 is transmitted to the D.sub.-- latch 215, which non inverting output is transmitted back to OA 214. Thus D.sub.-- latch 215 generates, at the rate of a sigma-delta clock existing on its clock input lead, a train of sigma-delta pulses which average voltage value corresponds to the analog signal to be converted. The non inverting input of OA 214 is generally connected to a reference voltage Vref which is fixed at a value being equal to (+V+0 V)/2, with +V and 0 V being the power supply voltages of D-latch 215. However, it appears practically impossible to have a value Vref being strictly equal to the ideal value (+V+-V)/2 and a difference of at least some millivolts still exists. This difference results in a DC component appearing in the codage at the output of latch 215 which disturbs the further signal processing operations which are carried out on the signal. Indeed, the effect of a DC component in the sigma-delta coding process appears as a non-linear distortion which spoils the further linear digital signal processing mechanisms which are used in telecommunication equipments, such as Data Circuit Terminating Equipments (DCE), equalization or the clock recovery processing systems.
Known solutions for suppressing the above DC components are based on an additional analog circuit which is connected to the positive input of OA 214, introducing a feedback value of the sigma-delta pulses so that to compensate for the DC component therein included. This solution appears however limited since it only achieves rejection rates about 40 dB approximately.
Another solution for the compensation of the DC component which is introduced during the sigma-delta pulses coding consists in using during the further digital signal processing operations carried out by the DSP processor a specific non-linear algorithm designed to handle this DC component. This solution appears much more accurate but unfortunately entails a substantial drawback since that algorithm would necessitate non-negligible digital signal processing resources from the DSP processor. Indeed, when the oversampling frequency increases, the digital resources requiring for such an algorithm tends to become high. For instance, in the case of a base-band or digital modem operating at a bit frequency of 72 kbps, and also with the assumption of an oversampling frequency of 144 Khz with a DSP operating at a 15 MHz rate, it appears that only about 100 elementary cycles of the digital processor are available for the processing of one given sample. Therefore, an additional algorithm for suppressing the DC component, although only requiring a few elementary cycles from the DSP processor, would however use-few percent of the whole digital processing resources.